![]() ![]() Let's say the user typed 129 and the program wants to convert that to binary. Generally, user input and output happen as strings of characters, and the program will then convert the strings of text to whatever format is needed. When a key is hit on the keyboard, there's a binary constant for each key 0-9 map to binary 0x30-0x39. ![]() See the examples to follow.ħ Verilog - Representation of Number Literals (cont.) Some examples: module number_test reg a = 8 sha6 initial $displayb ("a=", a) // number 0xA6 is signed, MSB of size (7) is one, so its negative // so to produce the 12 bit result, its sign extended with 1 s, thus //a=1111_1010_0110 reg b = 8 sh6a initial $displayb ("b=", b) // signed number 0圆A has MSB (7) is zero, its positive // so to produce the 12 bit result, its sign extended with 0 s, thus // b=0000_0110_1010 reg c = sha6 initial $displayb ("c=", c) //c is the signed number A6, but its MSB is zero as its 32 bits long // c=0000_1010_0110, not sign extended reg d = sh6a initial $displayb ("d=", d) //signed, unsized number 6A has MSB (31) zero so its positive: // 0000_0000_0000_0000_0000_0000_0110_1010 //assign the 32 bit value to 12 bits: // d=0000_0110_1010Ĩ Verilog - Representation of Number Literals (cont.) Some more examples: reg e = -8 sha6 initial $displayb ("e=", e) //0xA6 is signed, expanded to 8 bits with MSB (7) one: 1010_0110 //negating this with a minus sign: (2 s compliment) : 0101_1010 //now assign with sign extension: e=0000_0101_1010 //i.e.The computer does all its math in binary (or floating point binary which I'll ignore here). We need to be careful with how an explicit sign is interpreted. Beware!Ħ Verilog - Representation of Number Literals (cont.) Literal numbers can also carry a sign: -4 sd15 This is equivalent to -(4 sd15) or -(-1) or 1. If a signed number such as 9shA6, (8 bits in 9 bit vector) is assigned to a bigger vector the sign bit is lost and is not sign extended. reg p1 = 4 sha initial $displayb ("p1 signed =\t", p1) //p1 = 1111_1111_1010, bit 3 is the sign bit reg p2 = 5 sha initial $displayb ("p2 signed =\t", p2) //p2 = 0000_0000_1010, bit 3 was the sign bit, but was lost in extension When the value is assgined to a bigger vector, the sign indication, will force sign extension when the MSB of value is one. 8 ha //unsigned value extends to: sha //signed value extends to: If the MSB of the size is one and is signed, sign extension will occur. Signed values are not necessarily sign extended because the sign bit is the MSB of the size, not the MSB of the value. If is smaller than value MSB s of value are truncated with warning (tool dependent) If is larger than value MSB s of value are filled Regardless of MSB being 0 or 1, 0 filling is done Left-most Bit Expansion 0 0 extend 1 0 extend x X x or X extend z Z z or Z extendĤ Verilog - Representation of Number Literals(cont.) Some Examples: reg v = 8 b1011 initial $displayb ("v signed =\t", v) //v =, MSBs filled with zeros reg w = 3 b1011 initial $displayb ("w signed =\t", w) //w =, bit 3 truncated then 0 filled //generates Modelsim compile warning (Redundant digits in numeric literal) //Runs without warning or errorĥ Verilog - Representation of Number Literals (cont.) Literal numbers may be declared as signed: 4shf 4 bit number (1111) interpreted as a signed 2s complement value Decimal value is -1. radix Radix of the number b or B : binary o or O : octal h or H : hex d or D : decimal default is decimalĢ Verilog - Representation of Number Literals(cont.) Possible values for value are dependent on the radix Format Prefix Legal characters binary b 01xXzZ? octal o 0-7xXzZ? decimal d 0-9 hexadecimal h 0-9a-fA-FxXzZ? The underscore is a separator used to improve readability e.g.: is easily read as 0x2AE5 The character x or X represents unknown The character z or Z represents high impedance The character? or? same as Z (high impedance) The character? is also don t care to synthesisģ Verilog - Representation of Number Literals(cont.) If prefix is preceded by a number, number defines the bit width If no prefix given, number is assumed to be 32 bits Verilog expands to fill given working from LSB to MSB. A separator, single quote, not a backtick signed Indicates if the value is signed. Barbossa) Numbers are represented as: value ( indicates optional part) size The number of binary bits the number is comprised of. 1 Verilog - Representation of Number Literals. ![]()
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